Liquid crystal display device and electronic device including the same

ABSTRACT

A liquid crystal display device is provided in which the aperture ratio can be increased in a pixel including a thin film transistor in which an oxide semiconductor is used. In the liquid crystal display device, the thin film transistor including a gate electrode, a gate insulating layer and an oxide semiconductor layer which are provided so as to overlap with the gate electrode, and a source electrode and a drain electrode which overlap part of the oxide semiconductor layer is provided between a signal line and a pixel electrode which are provided in a pixel portion. The off-current of the thin film transistor is  1×10   13  A or less. A potential can be held only by a liquid crystal capacitor, without a capacitor which is parallel to a liquid crystal element, and a capacitor connected to the pixel electrode is not formed in the pixel portion.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductordevice including a field-effect transistor using an oxide semiconductor.

In this specification, a semiconductor device means all types of deviceswhich can function by utilizing semiconductor characteristics, and anelectro-optical device such as a liquid crystal display device, asemiconductor circuit, and an electronic device are all semiconductordevices.

BACKGROUND ART

A technique for forming thin film transistors using a semiconductor thinfilm formed over a substrate having an insulating surface has attractedattention. The thin film transistors are used for display devicestypified by liquid crystal televisions. A silicon-based semiconductormaterial is known as a material for a thin semiconductor film applicableto a thin film transistor. As another material, an oxide semiconductorhas attracted attention.

As a material for the oxide semiconductor, zinc oxide and a materialcontaining zinc oxide as its component are known. Further, a thin filmtransistor formed using an amorphous oxide (oxide semiconductor) havingan electron carrier concentration of less than 10¹⁸/cm³ is disclosed(Patent Documents 1 to 3).

REFERENCE Patent Document

[Patent Document 1] Japanese Published Patent Application No.2006-1655270

[Patent Document 2] Japanese Published Patent Application No.2006-165528

[Patent Document 3] Japanese Published Patent Application No.2006-165529

DISCLOSURE OF INVENTION

However, a difference from a stoichiometric composition of an oxidesemiconductor film occurs in the formation process, which becomes aproblem in some cases. For example, in the case where oxygen in a filmis excess or deficient, or the case where hydrogen contained as animpurity becomes an electron donor, electrical conductivity changes.

Even when having an electron carrier concentration of less than10¹⁸/cm³, an oxide semiconductor is a substantially n-type oxidesemiconductor, and an on-off ratio of the thin film transistor disclosedin the Patent Documents is only about 10³. Such a low on-off ratio ofthe thin film transistor is due to large off-current.

It is an object of one embodiment of the present invention to provide adisplay device including a thin film transistor having stable electriccharacteristics (e.g., an off-current is extremely reduced.).

One embodiment of the present invention is a liquid crystal displaydevice including a thin film transistor in which a channel region isformed using an oxide semiconductor which is an intrinsic orsubstantially intrinsic semiconductor obtained by removal of impuritiesserving as electron donors (donors) in the oxide semiconductor and whichhas a larger energy gap than a silicon semiconductor.

That is, one embodiment of the present invention is a liquid crystaldisplay device including a thin film transistor in which a channelregion is formed using an oxide semiconductor film. Hydrogen or an OHbond contained in the oxide semiconductor is extremely reduced so thathydrogen is contained at 5×10¹⁹/cm³ or less, preferably 5×10¹⁸/cm³ orless, more preferably 5×10¹⁷/cm³ or less in the oxide semiconductor, andthe carrier concentration of the oxide semiconductor film is set to5×10¹⁴/cm³ or less, preferably 5×10¹²/cm³ or less.

The energy gap of the oxide semiconductor is 2 eV or more, preferably2.5 eV or more, more preferably 3 eV or more and an impurity such ashydrogen which forms a donor is extremely reduced so that the carrierconcentration is 1×10¹⁴/cm³ or less, preferably 1×10¹²/cm³ or less.

When such a highly purified oxide semiconductor is used for a channelformation region of a thin film transistor, even in the case where thechannel width is 10 mm and the drain voltage is 10 V, the oxidesemiconductor operates so that the drain current is 1×10⁻¹³ A or less ata gate voltage of −5 V to 20 V.

One embodiment of the present invention disclosed in this specificationis a liquid crystal display device. In the liquid crystal displaydevice, a thin film transistor including a gate electrode, a gateinsulating layer which is provided so as to overlap the gate electrode,an oxide semiconductor layer which is provided so as to overlap the gateelectrode with the gate insulating layer interposed therebetween, and asource electrode and a drain electrode which are provided so as tooverlap part of the oxide semiconductor layer is provided between asignal line and a pixel electrode which are provided in a pixel portion.An auxiliary capacitor which is electrically connected to the pixelelectrode is not formed.

Another embodiment of the present invention disclosed in thisspecification is a liquid crystal display device. In the liquid crystaldisplay device, a thin film transistor includes a gate electrode, a gateinsulating layer which is provided so as to overlap the gate electrode,an oxide semiconductor layer which is provided so as to overlap the gateelectrode with the gate insulating layer interposed therebetween, and asource electrode and a drain electrode which are provided so as tooverlap part of the oxide semiconductor layer. The thin film transistoris provided between a signal line and a pixel electrode which are eachprovided in a plurality of subpixels in one pixel. An auxiliarycapacitor which is electrically connected to the pixel electrode is notformed.

Note that an auxiliary capacitor refers to a capacitor which isintentionally provided, and parasitic capacitance which is notintentionally provided may be formed.

According to one embodiment of the present invention, a capacitor tohold a signal voltage applied to a pixel is not necessarily providedbecause the off-current is reduced to 1×10⁻¹³ A or less. That is, sincean auxiliary capacitor is not necessarily provided in each pixel, theaperture ratio can be improved. In addition, a pixel using a thin filmtransistor according to one embodiment of the present invention can bekept in a certain state (a state where a video signal is written) andthus stable operation can be performed even in the case where a stillimage is displayed.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A and 1B are a top view and a cross-sectional view of a liquidcrystal display device.

FIGS. 2A and 2B are a top view and a cross-sectional view of a liquidcrystal display device.

FIGS. 3A to 3D are cross-sectional views illustrating a method formanufacturing a liquid crystal display device.

FIG. 4 shows Vg-Id characteristics of a thin film transistor in which anoxide semiconductor is used.

FIGS. 5A and 5B are photographs of a thin film transistor in which anoxide semiconductor is used.

FIGS. 6A and 6B show Vg-Id characteristics (temperature characteristics)of a thin film transistor in which an oxide semiconductor is used.

FIG. 7 illustrates a liquid crystal display device.

FIG. 8 is a longitudinal sectional view of a thin film transistor havingan inverted staggered structure in which an oxide semiconductor is used.

FIGS. 9A and 9B are energy band diagrams (schematic diagrams) along anA-A′ section illustrated in FIG. 8.

FIGS. 10A and 10B are energy band diagrams (schematic diagrams) along aB-B′ section illustrated in FIG. 8; FIG. 10A illustrates a state inwhich a positive voltage (+V_(G)) is applied to a gate (G1) and FIG. 10Billustrates a state in which a negative voltage (−V_(G)) is applied tothe gate (G1).

FIG. 11 shows a relation between the vacuum level and the work functionof a metal (ϕ_(M)) and a relation between the vacuum level and theelectron affinity (χ) of an oxide semiconductor.

FIGS. 12A and 12B each illustrate a liquid crystal display device.

FIGS. 13A and 13B each illustrate a liquid crystal display device.

FIGS. 14A and 14B illustrate a liquid crystal display device.

FIGS. 15A and 15B each illustrate a liquid crystal display device.

FIGS. 16A and 16B each illustrate a liquid crystal display device.

FIGS. 17A to 17C each illustrate an electronic device.

FIGS. 18A to 18C each illustrate an electronic device.

FIG. 19 illustrates a band structure between a source and a drain of asilicon MOS transistor.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail withreference to the accompanying drawings. The present invention is notlimited to the following description, and it is easily understood bythose skilled in the art that modes and details disclosed herein can bemodified in various ways without departing from the spirit and the scopeof the present invention. Therefore, the present invention is not to beconstrued as being limited to the content of the embodiments includedherein. Note that in the structures of the present invention describedbelow, the same reference numerals are used for the same portions andportions having similar functions in different drawings, and thedescription thereof is not repeated.

Note that the size, the thickness of a layer, or a region of eachstructure illustrated in drawings in this specification is exaggeratedfor simplicity in some cases. Therefore, embodiments of the presentinvention are not limited to such scales.

Note that the terms such as “first”, “second”, and “third” used in thisspecification are used in order to avoid confusion of structuralelements and do not mean limitation of the number of the structuralelements. Therefore, for example, the term “first” can be replaced withthe term “second”, “third”, or the like as appropriate.

Embodiment 1

An example is described below in which a pixel of a liquid crystaldisplay device is formed using a thin film transistor according to oneembodiment of the present invention. In this embodiment, in a liquidcrystal display device, a thin film transistor included in a pixel andan electrode (also referred to as a pixel electrode) connected to thethin film transistor will be shown and described as an example. Notethat a pixel includes elements provided in each pixel of a displaydevice, for example, a thin film transistor, an electrode functioning asa pixel electrode, a wiring for supplying an electric signal to theelement, and the like. Note that a pixel may include a color filter orthe like. For example, in a color display device including colorelements of R, G, and B, a minimum unit of an image is composed of threepixels of an R pixel, a G pixel, and a B pixel.

Note that when it is described that “A and B are connected”, the casewhere A and B are electrically connected to each other, and the casewhere A and B are directly connected to each other are included therein.Here, A and B are each an object (e.g., a device, an element, a circuit,a wiring, an electrode, a terminal, a conductive film, a layer, or thelike).

A storage capacitance is a combination of a capacitance of a liquidcrystal element and a capacitance of a capacitor which is providedseparately. The former is referred to as a liquid crystal capacitanceand the latter is referred to as an auxiliary capacitance fordistinction.

First, as an example of a pixel portion in a conventional liquid crystaldisplay device, a top view is illustrated in FIG. 2A. A thin filmtransistor illustrated in FIG. 2A has a kind of bottom-gate structurecalled an inverted staggered structure in which a wiring layer servingas a source electrode and a drain electrode is provided over an oxidesemiconductor layer overlapped with a gate electrode.

A pixel portion illustrated in FIG. 2A includes a first wiring 2101functioning as a scan line, a second wiring 2102A functioning as asignal line, an oxide semiconductor layer 2103, a capacitor line 2104,and a pixel electrode 2105. Moreover, the pixel portion in FIG. 2Aincludes a third wiring 2102B for electrically connecting the oxidesemiconductor layer 2103 and the pixel electrode 2105.

The first wiring 2101 also functions as a gate electrode of a thin filmtransistor 2106.

The second wiring 2102A also functions as one of a source electrode anda drain electrode of the thin film transistor 2106 and one electrode ofa capacitor.

The third wiring 2102B also functions as the other of the sourceelectrode and the drain electrode of the thin film transistor 2106.

The capacitor line 2104 functions as the other electrode of thecapacitor. Note that the first wiring 2101 and the capacitor line 2104are formed in the same layer, and the second wiring 2102A and the thirdwiring 2102B are formed in the same layer. In addition, the third wiring2102B and the capacitor line 2104 partly overlap with each other to forman auxiliary capacitor (a capacitor) of a liquid crystal element. Theoxide semiconductor layer 2103 included in the thin film transistor 2106is provided over the first wiring 2101 with a gate insulating film 2113(not illustrated) therebetween.

FIG. 2B illustrates a cross-sectional structure along chain line A1-A2in FIG. 2A.

In the cross-sectional structure illustrated in FIG. 2B, the firstwiring 2101 serving as the gate electrode and the capacitor line 2104are provided over a substrate 2111 with a base film 2112 therebetween.The gate insulating film 2113 is provided so as to cover the firstwiring 2101 and the capacitor line 2104. The oxide semiconductor layer2103 is provided over the gate insulating film 2113. Further, the secondwiring 2102A and the third wiring 2102B are provided over the oxidesemiconductor layer 2103, and an oxide insulating layer 2114 functioningas a passivation film is provided thereover. An opening portion isformed in the oxide insulating layer 2114. The pixel electrode 2105 andthe third wiring 2102B are connected to each other in the openingportion. A capacitor is formed by the third wiring 2102B and thecapacitor line 2104, using the gate insulating film 2113 as adielectric.

Note that the pixel illustrated in FIGS. 2A and 2B corresponds to one ofa plurality of pixels 701 arranged in a matrix over a substrate 700 asillustrated in FIG. 7. FIG. 7 illustrates a structure in which a pixelportion 702, a scan line driver circuit 703, and a signal line drivercircuit 704 are placed over the substrate 700. Whether the pixels 701are in a selected state or in a non-selected state is determined per rowin accordance with a scan signal supplied from the first wiring 101connected to the scan line driver circuit 703. The pixel 701 selected bythe scan signal is supplied with a video voltage (also referred to as animage signal, a video signal, or video data) from the wiring 2102Aconnected to the signal line driver circuit 704.

FIG. 7 illustrates the structure in which the scan line driver circuit703 and the signal line driver circuit 704 are provided over thesubstrate 700; alternatively, one of the scan line driver circuit 703and the signal line driver circuit 704 may be provided over thesubstrate 700. Only the pixel portion 702 may be provided over thesubstrate 700.

FIG. 7 illustrates an example in which the plurality of pixels 701 isarranged in a matrix (in stripe) in the pixel portion 702. Note that thepixels 701 are not necessarily arranged in a matrix and may be arrangedin a delta pattern or Bayer arrangement. As a display method of thepixel portion 702, a progressive method or an interlace method can beemployed. Note that color elements controlled in the pixel for colordisplay are not limited to three colors of R (red), G (green), and B(blue), and for example, RGBW (W corresponds to white), or RGB addedwith one or more of yellow, cyan, magenta, and the like may be employed.Further, the size of display regions may be different between dots ofcolor elements.

In FIG. 7, the first wirings 2101 and the second wirings 2102A areformed in accordance with the number of pixels in the row direction andcolumn direction. Note that the numbers of the first wirings 2101 andthe second wirings 2102A may be increased depending on the number ofsubpixels included in one pixel or the number of transistors in thepixel. The pixels 701 may be driven with the first wiring 2101 and thesecond wiring 2102A shared with some pixels.

Note that in FIG. 2A, the second wiring 2102A is rectangular;alternatively, the second wiring 2102A may surround the third wiring2102B (specifically, the second wiring 2102A may be in a U-shape orC-shape) so that the area of a region where carriers move is increasedto increase the amount of current flowing.

Note that a thin film transistor is an element having at least threeterminals of a gate, a drain, and a source. The thin film transistor hasa channel region between a drain region and a source region, and currentcan flow through the drain region, the channel region, and the sourceregion. Here, since the source and the drain of the transistor mayinterchange depending on the structure, the operating condition, and thelike of the transistor, it is difficult to define which is a source or adrain. Therefore, a region functioning as a source or a drain is notcalled the source or the drain in some cases. In such a case, forexample, one of the source and the drain is referred to as a firstterminal, a first electrode, or a first region and the other of thesource and the drain is referred to as a second terminal, a secondelectrode, or a second region in some cases.

Next, an example of a structure of a pixel portion according to oneembodiment of the present invention is illustrated in FIGS. 1A and 1B.FIG. 1A illustrates a structure in which a capacitor (an auxiliarycapacitor) is omitted from the structure of the pixel portion of theconventional example in FIG. 2A. Therefore, a capacitor line is notnecessary, and the third wiring 102B does not function as an electrodeof the capacitor. The third wiring 102B serves a wiring connected toonly a pixel electrode 105 as the source electrode or the drainelectrode, which leads to reduction in area. Thus, the aperture ratiocan be significantly increased.

Note that an example of a structure of a pixel portion in which acapacitor is omitted, which is one embodiment of the present invention,can have the same structure (except a capacitor) as the above-describedconventional example. Although a transistor having an inverted staggeredstructure is described as an example, a transistor having anotherstructure such as a bottom contact structure or a top gate structure maybe used.

In order to omit a capacitor from a pixel portion as described above,the potential of the pixel needs to be held only by a charged liquidcrystal element for a certain period. To realize this, the off-currentof a thin film transistor needs to be sufficiently reduced. One exampleof a manufacturing method of a thin film transistor to achieve thesecharacteristics is described with reference to FIGS. 3A to 3D.

A glass substrate can be used as the light-transmitting substrate 111. Abase film 112 is provided over the substrate 111 in order to preventdiffusion of impurities from the substrate 111 or improve adhesionbetween the substrate 111 and elements provided over the substrate 111.Note that the base film 112 is not necessarily provided.

Next, a conductive layer is formed over the base film 112. After that, afirst photolithography step is performed so that a resist mask is formedand unnecessary portions are removed by etching, whereby the firstwiring 101 is formed. At this time, etching is preferably performed sothat edges of the first wiring 101 are tapered. FIG. 3A is across-sectional view at this stage.

The first wiring 101 is preferably formed using a low-resistanceconductive material such as aluminum or copper. Since the use ofaluminum alone has disadvantages such as low heat resistance and atendency to be corroded, aluminum is preferably used in combination witha conductive material having heat resistance. As the conductive materialhaving heat resistance, it is possible to use an element selected fromtitanium, tantalum, tungsten, molybdenum, chromium, neodymium, andscandium; an alloy containing any of these elements as its component; analloy containing a combination of any of these elements; or a nitridecontaining any of these elements as its component.

Note that the wirings and the like included in the thin film transistorcan be formed by an inkjet method or a printing method. Since thewirings and the like can be manufactured without using a photomask, alayout of the transistor can be changed easily. Further, it is notnecessary to use a resist, so that material cost is reduced and thenumber of steps can be reduced. In addition, a resist mask and the likecan also be formed by an inkjet method or a printing method. Since aresist mask can be formed only over intended portions by an inkjetmethod or a printing method, cost can be reduced.

A resist mask having regions with a plurality of thicknesses (typically,two kinds of thicknesses) may be formed using a multi-tone mask to formwirings and the like.

Then, an insulating film (hereinafter referred to as a gate insulatingfilm 113) is formed over the first wiring 101.

In this embodiment, the gate insulating film 113 is formed using ahigh-density plasma CVD apparatus in which a microwave (2.45 GHz) isused. Here, a high-density plasma CVD apparatus refers to an apparatuswhich can realize a plasma density higher than or equal to 1×10¹¹/cm³.For example, plasma is generated by applying a microwave power higherthan or equal to 3 kW and lower than or equal to 6 kW so that aninsulating film is formed.

A monosilane gas (SiH₄), nitrous oxide (N₂O), and a rare gas areintroduced into a chamber as a source gas to generate high-densityplasma at a pressure higher than or equal to 10 Pa and lower than orequal to 30 Pa so that an insulating film is formed over a substrate.After that, the supply of a monosilane gas is stopped, and nitrous oxide(N₂O) and a rare gas are introduced without exposure to the air, so thatplasma treatment may be performed on a surface of the insulating film.The plasma treatment performed on the surface of the insulating film byintroducing nitrous oxide (N₂O) and a rare gas is performed at leastafter the insulating film is formed. The insulating film formed throughthe above process procedure has a small thickness, and reliability canbe ensured even when it has a thickness less than 100 nm, for example.

In forming the gate insulating film 113, the flow ratio of a monosilanegas (SiH₄) to nitrous oxide (N₂O) which are introduced into the chamberis in the range of 1:10 to 1:200. In addition, as a rare gas which isintroduced into the chamber, helium, argon, krypton, xenon, or the likecan be used. In particular, argon, which is inexpensive, is preferablyused.

Further, the insulating film formed using the high-density plasma CVDapparatus has excellent step coverage and the thickness thereof can becontrolled precisely.

The insulating film formed through the above process procedure isgreatly different from the insulating film formed using a conventionalparallel plate PCVD apparatus. The etching rate of the insulating filmformed through the above process procedure is lower than that of theinsulating film formed using the conventional parallel plate PCVDapparatus by 10% or more or 20% or more in the case where the etchingrates with the same etchant are compared to each other. Thus, it can besaid that the insulating film formed using the high-density plasma CVDapparatus is a dense film.

In this embodiment, a silicon oxynitride film (also referred to asSiO_(x)N_(y), where x>y>0) with a thickness of 100 nm formed using thehigh-density plasma CVD apparatus is used as the gate insulating film113.

As another formation method of the gate insulating film 113, asputtering method may be employed. It is needless to say that the gateinsulating film 113 is not limited to such a silicon oxide film and maybe formed with a single-layer structure or a layered structure ofanother insulating film such as a silicon oxynitride film, a siliconnitride film, an aluminum oxide film, or a tantalum oxide film.

Note that before the deposition of an oxide semiconductor, dust attachedto a surface of the gate insulating film 113 is preferably removed byreverse sputtering in which argon is used as a sputtering gas. Note thatas a sputtering gas, nitrogen, helium, or the like may be used insteadof argon. Alternatively, argon to which oxygen, hydrogen, N₂O, Cl₂, CF₄,or the like is added may be used as a sputtering gas.

Next, an oxide semiconductor film is formed over the gate insulatingfilm 113. The field-effect mobility of a transistor in which an oxidesemiconductor is used for a semiconductor layer can be higher than thatof a transistor in which amorphous silicon is used for a semiconductorlayer. Note that examples of the oxide semiconductor are zinc oxide(ZnO), tin oxide (SnO₂), and the like. Moreover, In, Ga, or the like canbe added to ZnO.

For the oxide semiconductor film, a thin film represented by thechemical formula, InMO₃(ZnO)_(m) (m>0) can be used. Note that M denotesone metal element or a plurality of metal elements selected from Ga, Al,Mn, and Co. Specifically, M may be Ga, Ga and Al, Ga and Mn, Ga and Co,or the like.

As the oxide semiconductor film, the following oxide semiconductors canalso be used: a four-component metal oxide such as anIn-Sn-Ga-Zn-O-based oxide semiconductor; a three-component metal oxidesuch as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-basedoxide semiconductor, an In-Al-Zn-O-based oxide semiconductor, aSn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxidesemiconductor, and a Sn-Al-Zn-O-based oxide semiconductor; atwo-component metal oxide such as an In-Zn-O-based oxide semiconductor,a Sn-Zn-O-based oxide semiconductor, an Al-Zn-O-based oxidesemiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-basedoxide semiconductor, an In-Mg-O-based oxide semiconductor, anIn-Ga-O-based oxide semiconductor; an In-O-based oxide semiconductor; aSn-O-based oxide semiconductor; and a Zn-O-based oxide semiconductor.Further, SiO₂ may be contained in the above oxide semiconductor. Here,an In-Ga-Zn-O-based oxide semiconductor means an oxide including indium(In), gallium (Ga), and zinc (Zn), and there is no particular limitationon the stoichiometric proportion. Further, the In-Ga-Zn-O-based oxidesemiconductor may contain an element other than In, Ga, and Zn.Furthermore, it is preferable that the energy gap of the oxidesemiconductor is 2 eV or more, preferably 2.5 eV or more, morepreferably 3 eV or more.

An In-Ga-Zn-O-based film is used as the oxide semiconductor. Here, atarget in which In₂O₃, Ga₂O₃, and ZnO are contained at a molar ratio of1:1:1 or 1:1:2 is used, and deposition is performed by a sputteringmethod. The oxide semiconductor is deposited under the followingconditions: the distance between the substrate and the target is 100 mm,the pressure is 0.6 Pa, the direct current (DC) power is 0.5 kW, and theatmosphere is an oxygen atmosphere (the proportion of the oxygen flow is100%). Note that a pulsed direct current (DC) power supply is preferablyused because powder substances (also referred to as particles or dust)generated in film deposition can be reduced and the film thickness canbe uniform.

In this case, the oxide semiconductor film is preferably formed whileremaining moisture in the treatment chamber is removed, in order toprevent hydrogen, hydroxyl group, or moisture from being contained inthe oxide semiconductor film.

In order to remove remaining moisture in the treatment chamber, anentrapment vacuum pump is preferably used. For example, a cryopump, anion pump, or a titanium sublimation pump is preferably used. Theevacuation unit may be a turbo molecular pump provided with a cold trap.In the deposition chamber which is evacuated with the cryopump, ahydrogen atom, a compound containing a hydrogen atom such as water(H₂O), and the like are removed, whereby the concentration of animpurity in the oxide semiconductor film formed in the depositionchamber can be reduced.

Next, a second photolithography step is performed so that a resist maskis formed and unnecessary portions are removed by etching, whereby theoxide semiconductor layer 103 is formed. The first heat treatment forthe oxide semiconductor layer may be performed on the oxidesemiconductor film that has not yet been processed into theisland-shaped oxide semiconductor layer. FIG. 3B is a cross-sectionalview at this stage.

Next, the oxide semiconductor layer is subjected to dehydration ordehydrogenation. The temperature of first heat treatment for dehydrationor dehydrogenation is higher than or equal to 400° C. and lower than orequal to 750° C., preferably higher than or equal to 425° C. and lowerthan or equal to 750° C. Note that the heat treatment may be performedfor one hour or shorter when the temperature of the heat treatment is425° C. or higher; the heat treatment is preferably performed for onehour or longer when the temperature is lower than 425° C. Here, thesubstrate is introduced into an electric furnace, which is one of heattreatment apparatuses, and heat treatment is performed on the oxidesemiconductor layer in a nitrogen atmosphere. Then, the oxidesemiconductor layer is not exposed to air, and a high-purity oxygen gas,a high-purity N₂O gas, or an ultra-dry air (having a dew point of lowerthan or equal to −40° C., preferably lower than or equal to −60° C.) isintroduced into the same furnace and cooling is performed. At this time,it is preferable that water, hydrogen, and the like be not contained inthe gas introduced. Alternatively, the purity of the gas which isintroduced into the heat treatment apparatus is preferably 6N (99.9999%)or more preferably 7N (99.9999%) or more (that is, the impurityconcentration in the gas is 1 ppm or less, or preferably 0.1 ppm orless).

Note that in this specification, heat treatment in the atmosphere of aninert gas such as nitrogen or a rare gas is referred to as heattreatment for dehydration or dehydrogenation. In this specification,dehydrogenation does not indicate elimination of only H₂ by heattreatment. For convenience, elimination of H, OH, and the like is calleddehydration or dehydrogenation.

The heat treatment apparatus is not limited to an electric furnace. Forexample, a rapid thermal annealing (RTA) apparatus such as a gas rapidthermal annealing (GRTA) apparatus or a lamp rapid thermal annealing(LRTA) apparatus can be used. An LRTA apparatus is an apparatus forheating an object to be processed by radiation of light (anelectromagnetic wave) emitted from a lamp such as a halogen lamp, ametal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressuresodium lamp, or a high pressure mercury lamp. Further, the LRTAapparatus may have not only a lamp but also a device for heating anobject to be processed by heat conduction or heat radiation from aheater such as a resistance heater. GRTA is a method of heat treatmentusing a high-temperature gas. As the gas, an inert gas that hardlyreacts with an object to be processed by heat treatment, such asnitrogen or a rare gas such as argon is used. The heat treatment may beperformed using such an RTA method at higher than or equal to 600° C.and lower than or equal to 750° C. for several minutes.

Further, after the first heat treatment for dehydration ordehydrogenation, heat treatment may be performed at 200° C. to 400° C.inclusive, preferably 200° C. to 300° C. inclusive, in an atmosphere ofan oxygen gas or an N₂O gas.

When the oxide semiconductor layer is subjected to heat treatment at400° C. to 750° C. inclusive, the dehydration or dehydrogenation of theoxide semiconductor layer can be achieved; thus, water (H₂O) can beprevented from being contained again in the oxide semiconductor layerlater. At the same time of the dehydration or dehydrogenation, an i-typeoxide semiconductor layer is changed into an oxygen-deficient oxidesemiconductor layer, i.e., an n-type (e.g., n⁻-type and n⁺-type) oxidesemiconductor layer. When an oxide insulating film which is in contactwith the n-type oxide semiconductor layer is formed, the oxidesemiconductor layer is brought into an oxygen-excess state. Accordingly,the oxide semiconductor layer becomes an i-type oxide semiconductorlayer again so as to have high resistance. The threshold voltage of thetransistor using such an oxide semiconductor layer is positive, so thatthe transistor shows so-called normally-off characteristics. It ispreferable for a transistor used in a semiconductor device such as adisplay device that the gate voltage be a positive threshold voltagethat is as close to 0 V as possible. In an active matrix display device,electric characteristics of a transistor included in a circuit areimportant and the performance of the display device depends on theelectrical characteristics. In particular, the threshold voltage of thetransistor is important. If the threshold voltage of the transistor isnegative, the transistor has so-called normally-on characteristics, thatis, current flows between a source electrode and a drain electrode evenwhen the gate voltage is 0 V, so that it is difficult to control thecircuit formed using the transistor. In the case of a transistor wherethe threshold voltage is positive but an absolute value of the thresholdvoltage is large, the transistor cannot perform a switching operation insome cases because driving voltage is not high enough. In the case of ann-channel transistor, it is preferable that a channel be formed anddrain current begin to flow after a positive gate voltage is applied. Atransistor in which a channel is not formed unless driving voltage israised and a transistor in which a channel is formed and drain currentflows even when a negative voltage is applied are unsuitable for atransistor used in a circuit.

In the first heat treatment, water, hydrogen, and the like are notpreferably contained in nitrogen or a rare gas such as helium, neon, orargon. It is preferable that the purity of nitrogen or the rare gas suchas helium, neon, or argon which is introduced into a heat treatmentapparatus be set to be 6N (99.9999%) or higher, preferably 7N(99.99999%) or higher.

Here, the oxide semiconductor that is made to be an intrinsic oxidesemiconductor or a substantially intrinsic oxide semiconductor (theoxide semiconductor that is highly purified) by removal of impuritiessuch as hydrogen is extremely sensitive to an interface state and aninterface electric charge; thus, an interface between the oxidesemiconductor and the gate insulating film is important. Therefore, thegate insulating film (GI) that is in contact with the highly-purifiedoxide semiconductor needs to have higher quality.

For example, by the above-described high-density plasma CVD method usinga microwave (2.45 GHz), an insulating film which is dense, has highwithstand voltage, and has high quality can be formed. Thehighly-purified oxide semiconductor and the high-quality gate insulatingfilm are in close contact with each other, whereby the interface statedensity can be reduced to obtain favorable interface characteristics.Needless to say, another film formation method such as a sputteringmethod or a plasma CVD method can be employed as long as the methodenables formation of a good-quality insulating film as a gate insulatingfilm. Further, an insulating film whose film quality and characteristicof an interface between the insulating film and an oxide semiconductorare improved by heat treatment which is performed after formation of theinsulating film may be formed as a gate insulating film. In any case,any insulating film may be used as long as the insulating film hascharacteristics of enabling reduction in interface state density of aninterface between the insulating film and an oxide semiconductor andformation of a favorable interface as well as having favorable filmquality as a gate insulating film.

Further, when an oxide semiconductor containing many impurities issubjected to a gate bias-temperature stress test (BT test) for 12 hoursunder conditions that the temperature is 85° C. and the voltage appliedto the gate is 2×10⁶ V/cm, a bond between the impurity and a maincomponent of the oxide semiconductor is cleaved by a high electric field(B: bias) and a high temperature (T: temperature), and a generateddangling bond induces drift of threshold voltage (Vth). In contrast, thepresent invention makes it possible to obtain a thin film transistorwhich is stable to a BT test by removal of impurities in an oxidesemiconductor, especially hydrogen, water, and the like as much aspossible to obtain a favorable characteristic of an interface betweenthe oxide semiconductor film and a gate insulating film as describedabove.

Then, a conductive film is formed from a metal material over the oxidesemiconductor film by a sputtering method or a vacuum evaporationmethod. Examples of a material for the conductive film are an elementselected from aluminum, chromium, tantalum, titanium, molybdenum, andtungsten; an alloy containing any of the above elements as itscomponent; and an alloy containing a combination of any of the aboveelements. Further, in the case where heat treatment is performed at 200°C. to 600° C. inclusive, the conductive film preferably has sufficientheat resistance to withstand heat treatment performed in thistemperature range. Since the use of Al alone brings disadvantages suchas low heat resistance and a tendency to be corroded, aluminum is usedin combination with a conductive material having heat resistance. Assuch a conductive material having heat resistance, any of the followingmaterials can be used: an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, and scandium; an alloycontaining any of these above elements as its component; an alloycontaining a combination of any of these elements; and a nitridecontaining any of these elements as its component.

Here, the conductive film has a single-layer structure of a titaniumfilm. The conductive film may have a two-layer structure, and a titaniumfilm may be stacked over an aluminum film. Alternatively, the conductivefilm may have a three-layer structure in which a titanium film, analuminum film containing neodymium (an Al-Nd film), and a titanium filmare stacked in this order. Further alternatively, the conductive filmmay have a single-layer structure of an aluminum film containingsilicon.

Next, a third photolithography step is performed so that a resist maskis formed and unnecessary portions are removed by etching, whereby thesecond wiring 102A and the third wiring 102B made of the conductive filmare formed. Wet etching or dry etching is employed as an etching methodat this time. For example, when a conductive film of titanium is etchedwith wet etching using an ammonia peroxide mixture (hydrogen peroxidewater at 31 wt %: ammonia water at 28 wt % : water=5:2:2), the oxidesemiconductor layer 103 can be left while the second wiring 102A and thethird wiring 102B are selectively etched. FIG. 3C is a cross-sectionalview at this stage.

An exposed region of the oxide semiconductor layer is sometimes etchedin the third photolithography step depending on the etching conditions.In this case, the thickness of the oxide semiconductor layer 103 in aregion between the second wiring 102A and the third wiring 102B issmaller than that of the oxide semiconductor layer over the first wiring101 in a region overlapping the second wiring 102A or the third wiring102B.

Then, the oxide insulating layer 114 is formed over the gate insulatingfilm 113, the oxide semiconductor layer 103, the second wiring 102A, andthe third wiring 102B. At this stage, part of the oxide semiconductorlayer 103 is in contact with the oxide insulating layer 114.

The oxide insulating layer 114 can be formed to a thickness of at least1 nm by a method with which impurities such as water and hydrogen arenot mixed into the oxide insulating layer as appropriate. In thisembodiment, a silicon oxide film is formed by a sputtering method as theoxide insulating layer. The substrate temperature in film deposition ishigher than or equal to room temperature and lower than or equal to 300°C., and is 100° C. in this embodiment. The silicon oxide film can beformed by a sputtering method in a rare gas (typically, argon)atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas(typically, argon) and oxygen. As a target for deposition, a siliconoxide target or a silicon target can be used. For example, with the useof a silicon target, a silicon oxide film can be formed by a sputteringmethod in an atmosphere of oxygen and a rare gas. As the oxideinsulating layer which is formed in contact with the oxide semiconductorlayer which is changed into an oxygen-deficient type and has lowresistance, an inorganic insulating film that does not includeimpurities such as moisture, a hydrogen ion, and OH⁻ and blocks entry ofthese impurities from the outside is used. Specifically, a silicon oxidefilm, a silicon nitride oxide film, an aluminum oxide film, or analuminum oxynitride film is used. Note that a target for depositionwhich is doped with phosphorus (P) or boron (B) is used, so that anoxide insulating layer to which phosphorus (P) or boron (B) is added canbe formed.

In this embodiment, the oxide insulating layer 114 is formed by a pulsedDC sputtering method using a columnar polycrystalline silicon targetdoped with boron that has a purity of 6N and a resistivity of 0.01 Ωcmin the following conditions: the distance between the substrate and thetarget (T-S distance) is 89 mm, the pressure is 0.4 Pa, thedirect-current (DC) power is 6 kW, and the atmosphere is an oxygenatmosphere (the oxygen flow rate is 100%). The thickness thereof is 300nm.

Note that the oxide insulating layer 114 is provided on and in contactwith a region serving as the channel formation region of the oxidesemiconductor layer and also functions as a channel protective layer.

In this case, the oxide insulating layer 114 is preferably formed whileremaining moisture in the treatment chamber is removed, in order toprevent hydrogen, hydroxyl group, or moisture from being contained inthe oxide semiconductor layer 103 and the oxide insulating layer 114.

In order to remove remaining moisture in the treatment chamber, anentrapment vacuum pump is preferably used. For example, a cryopump, anion pump, or a titanium sublimation pump is preferably used. Theevacuation unit may be a turbo molecular pump provided with a cold trap.In the deposition chamber which is evacuated with the cryopump, ahydrogen atom, a compound containing a hydrogen atom such as water(H₂O), and the like are removed, whereby the concentration of animpurity in the oxide insulating layer 114 formed in the depositionchamber can be reduced.

Next, second heat treatment (preferably at 200° C. to 400° C. inclusive,for example, 250° C. to 350° C. inclusive) is performed in an inert gasatmosphere. For example, the second heat treatment is performed at 250°C. for one hour in a nitrogen atmosphere. By the second heat treatment,heat is applied while part of the oxide semiconductor layer 103 is incontact with the oxide insulating layer 114.

When the second heat treatment is performed while the oxidesemiconductor layer 103 which is changed into an oxygen-deficient typeat the same time as elimination of hydrogen and the resistance of whichis reduced by the first heat treatment is in contact with the oxideinsulating layer 114, a region that is in contact with the oxideinsulating layer 114 is brought into an oxygen-excess state. Thus, theoxide semiconductor layer 103 is changed into a high-resistance (i-type)oxide semiconductor layer in the depth direction from the region that isin contact with the oxide insulating layer 114.

Further, the heat treatment may be performed at 100° C. to 200° C.inclusive for one hour to 30 hours inclusive in the air. For example,the heat treatment is performed at 150° C. for 10 hours. This heattreatment may be performed at a fixed heating temperature.Alternatively, the following change in the heating temperature may beconducted plural times repeatedly: the heating temperature is increasedfrom room temperature to a temperature of 100° C. to 200° C. inclusiveand then decreased to room temperature. Further, this heat treatment maybe performed before formation of the oxide insulating film under areduced pressure. Under the reduced pressure, the heat treatment timecan be shortened. With such heat treatment, hydrogen is introduced fromthe oxide semiconductor layer to the oxide insulating layer; thus, anormally-off thin film transistor can be obtained. Therefore,reliability of the semiconductor device can be improved.

Then, an opening portion 121 is formed in the oxide insulating layer 114through a fourth photolithography step and an etching step, and alight-transmitting conductive film is formed. The light-transmittingconductive film is formed using indium oxide (In₂O₃), indium tin oxide(In₂O₃—SnO₂, hereinafter abbreviated as ITO), or the like by asputtering method, a vacuum evaporation method, or the like.Alternatively, an Al-Zn-O-based film containing nitrogen, that is, anAl-Zn-O-N-based film, a Zn-O-based film containing nitrogen, or aSn-Zn-O-based film containing nitrogen may be used. Note that thecomposition ratio (atomic %) of zinc in the Al-Zn-O-N-based film is lessthan or equal to 47 atomic % and is higher than that of aluminum in thefilm; the composition ratio (atomic %) of aluminum in the film is higherthan that of nitrogen in the film. Such a material is etched with ahydrochloric acid-based solution. However, since a residue is easilygenerated particularly in etching ITO, indium zinc oxide (In₂O₃—ZnO) maybe used to improve etching process ability.

Note that the unit of the percentage of components in thelight-transmitting conductive film is atomic percent (atomic %), and thepercentage of components is evaluated by analysis using an electronprobe X-ray microanalyzer (EPMA).

Next, a fifth photolithography step is performed so that a resist maskis formed and unnecessary portions are removed by etching, therebyforming the pixel electrode 105. FIG. 3D is a cross-sectional view atthis stage.

In such a manner, the pixel including the thin film transistor 106 withlow off-current can be manufactured. Moreover, the pixels are arrangedin a matrix to form a pixel portion, whereby one of substrates formanufacturing an active-matrix liquid crystal display device can beobtained. In this specification, such a substrate is referred to as anactive-matrix substrate for convenience.

Note that in an active-matrix liquid crystal display device, pixelelectrodes arranged in a matrix are driven so that a display pattern isformed on a screen. Specifically, voltage is applied between a selectedpixel electrode and a counter electrode corresponding to the pixelelectrode, so that a liquid crystal layer provided between the pixelelectrode and the counter electrode is optically modulated and thisoptical modulation is recognized as a display pattern by an observer. Adisplay element such as a liquid crystal element is provided over thepixel electrode 105.

As described above, the structure described in this embodiment, in whicha capacitor is omitted, makes it possible to increase the aperture ratioof a pixel including a thin film transistor in which an oxidesemiconductor is used. Thus, a liquid crystal display device can includea high definition display portion.

This embodiment can be implemented in combination with any of thestructures described in the other embodiments as appropriate.

Embodiment 2

According to one embodiment of the present invention, impurities to bedonors (or acceptors) of carriers in an oxide semiconductor are reducedto a very low level, whereby the oxide semiconductor is made to beintrinsic or substantially intrinsic, and the oxide semiconductor isused for a thin film transistor. In this embodiment, measured values ofoff-current using a test element group (also referred to as a TEG) willbe described below.

FIG. 4 shows initial characteristics of a thin film transistor withL/W=3 μm/10000 μm in which 200 thin film transistors each with L/W=3μm/50 μm are connected in parallel. In addition, a top view is shown inFIG. 5A and a partially enlarged top view thereof is show in FIG. 5B.The region enclosed by a dotted line in FIG. 5B is a thin filmtransistor of one stage with L/W=3 μm/50 μm and Lov=1.5 μm. In order tomeasure initial characteristics of the thin film transistor, thechanging characteristics of the source-drain current (hereinafterreferred to as a drain current or Id), i.e., Vg-Id characteristics, weremeasured, under the conditions where the substrate temperature was setto room temperature, the voltage between source and drain (hereinafter,a drain voltage or Vd) was set to 10 V, and the voltage between sourceand gate (hereinafter, a gate voltage or Vg) was changed from −20 V to+20 V. Note that FIG. 4 shows Vg in the range of from −20 V to +5 V.

As shown in FIG. 4, the thin film transistor having a channel width W of10000 μm has an off-current of 1×10⁻¹³ A or less at Vd of 1 V and 10 V,which is less than or equal to the resolution (100 fA) of a measurementdevice (a semiconductor parameter analyzer, Agilent 4156C manufacturedby Agilent Technologies Inc.).

A method for manufacturing the thin film transistor used for themeasurement is described.

First, a silicon nitride film was formed as a base layer over a glasssubstrate by a CVD method, and a silicon oxynitride film was formed overthe silicon nitride film. A tungsten layer was formed as a gateelectrode layer over the silicon oxynitride film by a sputtering method.Here, the gate electrode layer was formed by selectively etching thetungsten layer.

Then, a silicon oxynitride film having a thickness of 100 nm was formedas a gate insulating layer over the gate electrode layer by a CVDmethod.

Then, an oxide semiconductor film having a thickness of 50 nm was formedover the gate insulating layer by a sputtering method using anIn-Ga-Zn-O-based metal oxide target (at a molar ratio ofIn₂O₃:Ga₂O₃:ZnO=1:1:2). Here, an island-shaped oxide semiconductor layerwas formed by selectively etching the oxide semiconductor film.

Then, first heat treatment was performed on the oxide semiconductorlayer in a nitrogen atmosphere in a clean oven at 450° C. for 1 hour.

Then, a titanium layer (having a thickness of 150 nm) was formed as asource electrode layer and a drain electrode layer over the oxidesemiconductor layer by a sputtering method. Here, the source electrodelayer and the drain electrode layer were formed by selectively etchingthe titanium layer such that 200 thin film transistors each having achannel length L of 3 μm and a channel width W of 50 μm were connectedin parallel to obtain a thin film transistor with L/W=3 μm/10000 μm.

Then, a silicon oxide film having a thickness of 300 nm was formed as aprotective insulating layer in contact with the oxide semiconductorlayer by a reactive sputtering method. Opening portions were formed overthe gate electrode layer, the source electrode layer, and the drainelectrode layer by selectively etching the silicon oxide film. Afterthat, second heat treatment was performed in a nitrogen atmosphere at250° C. for 1 hour.

Then, heat treatment was performed at 150° C. for 10 hours before themeasurement of Vg-Id characteristics.

Through the above process, a bottom-gate thin film transistor wasmanufactured.

The reason why the off-current of the thin film transistor isapproximately 1×10⁻¹³ A as shown in FIG. 4 is that the concentration ofhydrogen in the oxide semiconductor layer could be sufficiently reducedin the above manufacturing process. The concentration of hydrogen in theoxide semiconductor layer is 5×10¹⁹ atoms/cm³ or less, preferably 5×10¹⁸atoms/cm³ or less, more preferably 5×10¹⁷ atoms/cm³ or less. Note thatthe concentration of hydrogen in the oxide semiconductor layer wasmeasured by secondary ion mass spectrometry (SIMS).

Although the example of using an In-Ga-Zn-O-based oxide semiconductor isdescribed, this embodiment is not particularly limited thereto. Asanother oxide semiconductor material, a four-component metal oxide filmsuch as an In-Sn-Ga-Zn-O film; a three-component metal oxide film suchas an In-Ga-Zn-O film, an In-Sn-Zn-O film, an In-Al-Zn-O film, aSn-Ga-Zn-O film, an Al-Ga-Zn-O film, or a Sn-Al-Zn-O film; or atwo-component metal oxide film such as an In-Zn-O film, a Sn-Zn-O film,an Al-Zn-O film, a Zn-Mg-O film, a Sn-Mg-O film, or an In-Mg-O film; anIn-O film, a Sn-O film, or a Zn-O film can be used for the oxidesemiconductor film. Furthermore, as an oxide semiconductor material, anIn-Al-Zn-O-based oxide semiconductor mixed with AlO_(x) of 2.5 wt % to10 wt % or an In-Zn-O-based oxide semiconductor mixed with SiO_(x) of2.5 wt % to 10 wt % can be used.

The carrier concentration of the oxide semiconductor layer which ismeasured by a carrier measurement device is preferably less than orequal to 1.45×10¹⁰/cm³, which is intrinsic carrier concentration ofsilicon. Specifically, the carrier concentration is 5×10¹⁴/cm³ or less,preferably 5×10¹²/cm³ or less. In other words, the carrier concentrationof the oxide semiconductor layer can be made as close to zero aspossible.

The thin film transistor can also have a channel length L of 10 nm to1000 nm inclusive, which enables an increase in circuit operation speed,and the off-current is extremely small, which enables a furtherreduction in power consumption.

In addition, in circuit design, the oxide semiconductor layer can beregarded as an insulator when the thin film transistor is in an offstate.

After that, the temperature characteristics of off-current of the thinfilm transistor manufactured in this embodiment were evaluated.Temperature characteristics are important in considering theenvironmental resistance, maintenance of performance, or the like of anend product in which the thin film transistor is used. It is to beunderstood that a smaller amount of change is more preferable, whichincreases the degree of freedom for product designing.

For the temperature characteristics, the Vg-Id characteristics wereobtained using a constant-temperature chamber under the conditions wheresubstrates provided with thin film transistors were kept at respectiveconstant temperatures of −30° C., 0° C., 25° C., 40° C., 60° C., 80° C.,100° C., and 120° C., the drain voltage was set to 6 V, and the gatevoltage was changed from −20 V to +20V.

FIG. 6A shows Vg-Id characteristics measured at the above temperaturesand superimposed on one another, and FIG. 6B shows an enlarged view of arange of off-current enclosed by a dotted line in FIG. 6A. The rightmostcurve indicated by an arrow in the diagram is a curve obtained at −30°C.; the leftmost curve is a curve obtained at 120° C.; and curvesobtained at the other temperatures are located therebetween. Thetemperature dependence of on-currents can hardly be observed. On theother hand, as clearly shown also in the enlarged view of FIG. 6B, theoff-currents are less than or equal to 1×10⁻¹² A, which is near theresolution of the measurement device, at all temperatures except in thevicinity of a gate voltage of 20 V, and the temperature dependencethereof is not observed. In other words, even at a high temperature of120° C., the off-current is kept less than or equal to 1×10⁻¹² A, andgiven that the channel width W is 10000 μm, it can be seen that theoff-current is significantly small.

A thin film transistor including a purified oxide semiconductor(purified OS) shows almost no dependence of off-current on temperature.It can be said that an oxide semiconductor does not show temperaturedependence when purified because the conductivity type becomes extremelyclose to an intrinsic type and the Fermi level is located in the middleof the forbidden band, as illustrated in the energy band diagram of FIG.9A. This also results from the fact that the oxide semiconductor has anenergy gap of 3 eV or more and includes very few thermally excitedcarriers. In addition, the source region and the drain region are in adegenerated state, which is also a factor for showing no temperaturedependence. The thin film transistor is mainly operated with carrierswhich are injected from the degenerated source region to the oxidesemiconductor, and the above characteristics (independence ofoff-current on temperature) can be explained by independence of carrierconcentration on temperature. Further, this extremely low off-currentwill be described with reference to energy band diagrams below.

FIG. 8 is a longitudinal sectional view of an inverted staggered thinfilm transistor in which an oxide semiconductor is used. An oxidesemiconductor layer (OS) is provided over a gate electrode (GE1) with agate insulating film (GI) therebetween, and a source electrode (S) and adrain electrode (D) are provided thereover.

FIGS. 9A and 9B are energy band diagrams (schematic diagrams) along anA-A′ section illustrated in FIG. 8. FIG. 9A shows a case where thesource and the drain have voltage of the same potential (V_(D)=0 V).FIG. 9B shows a case where positive potential is applied to the drain(V_(D)>0 V) whereas positive potential is not applied to the source.

FIGS. 10A and 10B are energy band diagrams (schematic diagrams) along aB-B′ section illustrated in FIG. 8. FIG. 10A shows a state wherepositive potential (+V_(G)) is applied to a gate (G1), that is, a casewhere the thin film transistor is in an on state where carriers(electrons) flow between the source and the drain. FIG. 10B shows astate where negative potential (−V_(G)) is applied to the gate (G1),that is, a case where the thin film transistor is in an off state (whereminority carriers do not flow).

FIG. 11 shows relation between the vacuum level and the work function ofa metal (φ_(M)) and relation between the vacuum level and the electronaffinity (χ) of an oxide semiconductor.

At normal temperature, electrons in the metal degenerate and the Fermilevel is positioned in the conduction band. On the other hand, aconventional oxide semiconductor is generally of n-type, and the Fermilevel (E_(F)) in that case is positioned closer to the conduction bandand is away from the intrinsic Fermi level (E_(i)) that is located inthe middle of the band gap. Note that it is known that some hydrogen inthe oxide semiconductor form a donor and might be a factor that causesan oxide semiconductor to be an n-type oxide semiconductor.

In contrast, the oxide semiconductor according to the present inventionis an oxide semiconductor that is made to be an intrinsic (i-type)semiconductor or made to be as close to an intrinsic semiconductor aspossible by being highly purified not by addition of an impurity but byremoval of hydrogen that is an n-type impurity so that as fewimpurities, which are not main components of the oxide semiconductor, aspossible are contained. In other words, the oxide semiconductoraccording to the present invention has a feature in that it is made tobe an i-type (intrinsic) semiconductor or made to be close thereto bybeing highly purified by removal of impurities such as hydrogen or wateras much as possible. As a result, the Fermi level (E_(F)) can be at thesame level as the intrinsic Fermi level (E_(i)).

It is said that the electron affinity (χ) of an oxide semiconductor is4.3 eV in the case where the band gap (Eg) thereof is 3.15 eV. The workfunction of titanium used for forming the source and drain electrodes issubstantially equal to the electron affinity (χ) of the oxidesemiconductor. In the case where titanium is used for the source anddrain electrodes, the Schottky electron barrier is not formed at aninterface between the metal and the oxide semiconductor.

In other words, an energy band diagram (a schematic diagram) like FIG.9A is obtained in the case where a metal and an oxide semiconductor arein contact with each other when the work function of the metal (ϕ_(M))and the electron affinity (χ) of the oxide semiconductor aresubstantially equal.

In FIG. 9B, a black circle (●) represents an electron. When positivepotential is applied to the drain, the electron is injected into theoxide semiconductor over the barrier (h) and flows toward the drain. Inthat case, the height of the barrier (h) changes depending on the gatevoltage and the drain voltage. In the case where positive drain voltageis applied, the height of the barrier (h) is smaller than the height ofthe barrier (h) in FIG. 9A of the case where no voltage is applied; thatis, the height of the barrier (h) is smaller than half of the band gap(Eg).

In this case, as shown in FIG. 9A, the electron moves along the lowestpart of the oxide semiconductor, which is energetically stable, at aninterface between the gate insulating film and the highly-purified oxidesemiconductor.

In FIG. 9B, when negative potential (reverse bias) is applied to thegate (G1), the number of holes that are minority carriers issubstantially zero; thus, the current value becomes a value as close tozero as possible.

For example, even when the thin film transistor has a channel width W of1×10⁴ um and a channel length of 3 μm, an off-current of 10⁻¹³ A or lessand a subthreshold value (S value) of 0.1 V/dec. (the thickness of thegate insulating film: 100 nm) can be obtained.

FIG. 19 is a band structure of a transistor formed using a siliconsemiconductor. The intrinsic carrier concentration of a siliconsemiconductor is 1.45×10¹⁰/cm³ (300 K) and carriers exist even at roomtemperature. This means that thermally excited carriers exist even atroom temperature. A silicon wafer to which an impurity such asphosphorus or boron is added is used practically. Therefore, inpractice, 1×10¹⁴/cm³ or more carriers exist in a silicon semiconductor,and the carriers contribute to conduction between the source and thedrain. Furthermore, the band gap of a silicon semiconductor is 1.12 eV,and thus the off-current of a transistor including a siliconsemiconductor significantly changes depending on temperature.

Therefore, not by simply using an oxide semiconductor having a wide bandgap for a transistor but by highly purifying the oxide semiconductorsuch that an impurity other than a main component can be prevented frombeing contained therein as much as possible so that the carrierconcentration becomes 1×10¹⁴/cm³ or less, preferably 1×10¹²/cm³ or less,carriers to be thermally excited at a practical operation temperaturecan be eliminated, and the transistor can operate only with carriersthat are injected from the source side. This makes it possible todecrease the off-current to 1×10⁻¹³ A or less and to obtain a transistorwhose off-current hardly changes with a change in temperature and whichis capable of extremely stable operation.

In the case where a memory circuit (memory element) or the like ismanufactured using a thin film transistor having such an extremely smalloff-current, there is very little leakage. Therefore, memory data can bestored for a longer period of time. Similarly in a liquid crystaldisplay device and the like, leakage from a storage capacitor through athin film transistor can be suppressed; therefore, a potential of apixel can be held only by a liquid crystal capacitor, without anauxiliary capacitor.

This embodiment can be implemented in combination with any of thestructures described in the other embodiments as appropriate.

Embodiment 3

In this embodiment, a structure and operation of a pixel that can beapplied to a liquid crystal display device will be described.

FIG. 12A illustrates an example of a pixel configuration that can beapplied to a liquid crystal display device. A pixel 3880 includes atransistor 3881, a liquid crystal element 3882, and a capacitor 3883. Agate of the transistor 3881 is electrically connected to a wiring 3885.A first terminal of the transistor 3881 is electrically connected to awiring 3884. A second terminal of the transistor 3881 is electricallyconnected to a first terminal of the liquid crystal element 3882. Asecond terminal of the liquid crystal element 3882 is electricallyconnected to a wiring 3887. A first terminal of the capacitor 3883 iselectrically connected to the first terminal of the liquid crystalelement 3882. A second terminal of the capacitor 3883 is electricallyconnected to a wiring 3886.

The wiring 3884 can function as a signal line. The signal line is awiring for transmitting a signal voltage, which is input from theoutside of the pixel, to the pixel 3880. The wiring 3885 can function asa scan line. The scan line is a wiring for controlling on/off of thetransistor 3881. The wiring 3886 can function as a capacitor line. Thecapacitor line is a wiring for applying a predetermined voltage to thesecond terminal of the capacitor 3883. The transistor 3881 can functionas a switch. The capacitor 3883 can function as an auxiliary capacitor.The capacitor is an auxiliary capacitor with which the signal voltagecontinues to be applied to the liquid crystal element 3882 even when theswitch is off. The wiring 3887 can function as a counter electrode. Thecounter electrode is a wiring for applying a predetermined voltage tothe second terminal of the liquid crystal element 3882. Note that afunction of each wiring is not limited to the above, and each wiring canhave a variety of functions. For example, by changing a voltage appliedto the capacitor line, a voltage applied to the liquid crystal elementcan be adjusted.

FIG. 12B illustrates another example of a pixel configuration that canbe applied to a liquid crystal display device. The example of the pixelconfiguration in FIG. 12B is the same as that in FIG. 12A, except thatthe wiring 3887 is omitted and the second terminal of the liquid crystalelement 3882 and the second terminal of the capacitor 3883 areelectrically connected to each other. The example of the pixelconfiguration in FIG. 12B can be applied particularly to the case ofusing a liquid crystal element with a horizontal electric field mode(including an IPS mode and FFS mode). This is because in the horizontalelectric field mode liquid crystal element, the second terminal of theliquid crystal element 3882 and the second terminal of the capacitor3883 can be formed over one substrate, and thus it is easy toelectrically connect the second terminal of the liquid crystal element3882 and the second terminal of the capacitor 3883. With the pixelconfiguration in FIG. 12B, the wiring 3887 can be omitted, whereby amanufacturing process can be simplified and manufacturing cost can bereduced.

Here, a pixel portion including the thin film transistor described inEmbodiment 1 is illustrated in FIGS. 13A and 13B. FIG. 13A illustrates astructure in which the capacitor 3883 is omitted from the structureillustrated in FIG. 12A. In addition, FIG. 13B is a structure in whichthe capacitor 3883 is omitted from the structure illustrated in FIG.12B, and the second terminal of the liquid crystal element is connectedto a common wiring 889. As described in Embodiment 2, when a thin filmtransistor with sufficiently low off-current is used, a potential can beheld only by a liquid crystal capacitor, without a capacitor (anauxiliary capacitor) which is parallel to a liquid crystal element.Needless to say, a capacitor may be provided similarly to theabove-described comparative example, and the size thereof can bereduced. Further, a capacitance of an auxiliary capacitor which issmaller than a capacitance of a liquid crystal element may be formed. Inthis embodiment, a pixel configuration in which a capacitor is omittedis described below.

FIG. 14A illustrates a circuit configuration in the case where aplurality of pixels with the structure illustrated in FIG. 13A isarranged in a matrix. FIG. 14A is a circuit diagram illustrating fourpixels among a plurality of pixels included in the display portion. Apixel placed in an i-th column and a j-th row (i and j are each anatural number) is represented as a pixel 880_i, j, and a wiring 884_iand a wiring 885_j are electrically connected to the pixel 880_i, j.Similarly, a pixel 880_i+1, j is electrically connected to a wiring884_i+1 and the wiring 885_j. Similarly, a pixel 880_i, j+1 iselectrically connected to the wiring 884_i and a wiring 885_j+1.Similarly, a pixel 880_i+1, j+1 is electrically connected to the wiring884_i+1 and the wiring 885_j+1. Note that each of the wirings can beshared with a plurality of pixels in the same column or the same row. Inthe pixel configuration in FIG. 14A, the wiring 887 is a counterelectrode. Since the counter electrode is common to all the pixels, thewiring 887 is not indicated by the natural number i or j. Further, sincethe pixel configuration in FIG. 13B can also be used, the wiring 887 isnot essential even in a structure where the wiring 887 is provided, andthe wiring 887 can be omitted when another wiring serves as the wiring887, for example.

The pixel configuration in FIG. 14A can be driven by a variety ofmethods. In particular, when the pixels are driven by a method calledalternating-current driving, degradation (burn-in) of the liquid crystalelement can be suppressed. FIG. 14B is a timing chart of voltagesapplied to each wiring in the pixel configuration in FIG. 14A in thecase where dot inversion driving which is a kind of alternating-currentdriving is performed. By the dot inversion driving, flickers seen whenthe alternating-current driving is performed can be suppressed. Notethat FIG. 14B illustrates a signal 985_j input to the wiring 885_j, asignal 985_j+1 input to the wiring 885_j+1, a signal 984_i input to thewiring 884_j, and a signal 984_j+1 input to the wiring 884_j+1.

In the pixel configuration in FIG. 14A, a switch in a pixel electricallyconnected to the wiring 885_j is brought into a selection state (an onstate) in a j-th gate selection period in one frame period, and broughtinto a non-selection state (an off state) in the other periods. Then, a(j+1)-th gate selection period is provided after the j-th gate selectionperiod. By performing sequential scanning in this manner, all the pixelsare sequentially selected in one frame period. In the timing chart inFIG. 14B, the switch in the pixel is brought into a selection state whenthe voltage is set to high level, and the switch is brought into anon-selection state when the voltage is set to low level.

In the timing chart in FIG. 14B, in the j-th gate selection period in ak-th frame (k is a natural number), a positive signal voltage is appliedto the wiring 884_i used as a signal line, and a negative signal voltageis applied to the wiring 884_i+1. Then, in the (j+1)-th gate selectionperiod in the k-th frame, a negative signal voltage is applied to thewiring 884_i, and a positive signal voltage is applied to the wiring884_i+1. After that, signals whose polarity is reversed in each gateselection period are alternately supplied to each of the signal lines.Thus, in the k-th frame, the positive signal voltage is applied to thepixel 880_i, j and the pixel 880_+1, j+1, and the negative signalvoltage is applied to the pixel 880_i+1, j and the pixel 880_i, j+1.Then, in a (k+1)-th frame, a signal voltage whose polarity is oppositeto that of the signal voltage written in the k-th frame is written toeach pixel. Thus, in the (k+1)-th frame, the positive signal voltage isapplied to the pixel 880_i+1, j and the pixel 880_i, j+1, and thenegative signal voltage is applied to the pixel 880_i, j and the pixel880_i+1, j+1. The dot inversion driving is a driving method in whichsignal voltages whose polarity is different between adjacent pixels areapplied in one frame and the polarity of the signal voltage for onepixel is reversed in each frame as described above. By the dot inversiondriving, flickers seen when the entire or part of an image to bedisplayed is uniform can be reduced while degradation of the liquidcrystal element is suppressed. Although only the polarity of the signalvoltages for the wirings 884 is shown in the timing chart, the signalvoltages can actually have a variety of values in the polarity shown.Here, the case where the polarity is reversed per dot (per pixel) isdescribed; the polarity can be reversed per a plurality of pixelswithout limitation to the above. For example, when the polarity ofsignal voltages to be written is reversed per two gate selectionperiods, power consumed by writing the signal voltages can be reduced.Alternatively, the polarity can be reversed per column (source lineinversion) or per row (gate line inversion).

In this case, so-called overdriving may be performed in which anoverdrive voltage is applied to the pixel portion and the response speedof the liquid crystal element is increased to suppress blur. Thus, whena moving image is displayed, the movement thereof can be displayedclearly.

Specifically, in the case where a capacitor which is parallel to aliquid crystal element is not provided as in one embodiment of thepresent invention, there are cases where after writing data to thepixel, dielectric constant is changed in accordance with a change in astate of liquid crystal and a capacitance of the liquid crystal itselfis changed, whereby a potential held by the pixel is changed; therefore,overdriving is an effective driving method.

Next, a pixel configuration and a driving method that are preferablyused particularly by a liquid crystal element with a vertical alignment(VA) mode typified by an MVA mode or a PVA mode will be described. TheVA mode has advantages that a rubbing process is not necessary inmanufacturing, the amount of light leakage is small in displaying blackimages, the level of drive voltage is low, and the like; however, the VAmode has a problem in that the quality of images deteriorates when ascreen is viewed from an angle (i.e., the viewing angle is small). Inorder to increase the viewing angle in the VA mode, a pixelconfiguration in which one pixel includes a plurality of subpixels asillustrated in FIGS. 15A and 15B is effective. Pixel configurationsillustrated in FIGS. 15A and 15B are examples of the case where a pixelincludes two subpixels (a first subpixel 1080-1 and a second subpixel1080-2). Note that the number of subpixels in one pixel is not limitedto two and can be other numbers. As the number of subpixels becomeslarger, the viewing angle can be further increased. A plurality ofsubpixels can have the same circuit configuration. Here, the case isdescribed in which all the subpixels have the circuit configuration inFIG. 13A. The first subpixel 1080-1 includes a transistor 1081-1 and aliquid crystal element 1082-1. The connection relation is the same asthat in the circuit configuration in FIG. 13A. Similarly, the secondsubpixel 1080-2 includes a transistor 1081-2 and a liquid crystalelement 1082-2. The connection relation is the same as that in thecircuit configuration in FIG. 13A.

The pixel configuration in FIG. 15A includes, for two subpixels includedin one pixel, two wirings 1085 (a wiring 1085-1 and a wiring 1085-2)used as scan lines and one wiring 1084 used as a signal line. When thesignal line is shared with two subpixels in such a manner, the apertureratio can be increased. Further, a signal line driver circuit can besimplified, so that manufacturing cost can be reduced. Moreover, thenumber of connections between a liquid crystal panel and a drivercircuit IC can be reduced, so that the yield can be increased. The pixelconfiguration in FIG. 15B includes, for two subpixels included in onepixel, one wiring 1085 used as a scan line and two wirings 1084 (awiring 1084-1 and a wiring 1084-2) used as signal lines. When the scanline is shared with two subpixels in such a manner, the aperture ratiocan be increased. Further, the total number of scan lines can bereduced, so that one gate line selection period per pixel can besufficiently long even in a high-definition liquid crystal panel, and anappropriate signal voltage can be written to each pixel.

FIGS. 16A and 16B each schematically illustrate an example of electricalconnection of elements in the case where the liquid crystal element inthe pixel configuration in FIG. 15B is replaced with the shape of apixel electrode. In FIG. 16A, a first pixel electrode 1088-1 correspondsto a first terminal of the liquid crystal element 1082-1 in FIG. 15B,and a second pixel electrode 1088-2 corresponds to a first terminal ofthe liquid crystal element 1082-2 in FIG. 15B. That is, the first pixelelectrode 1088-1 is electrically connected to one of a source and adrain of the transistor 1081-1, and the second pixel electrode 1088-2 iselectrically connected to one of a source and a drain of the transistor1081-2. In FIG. 16B, the connection relation between the pixel electrodeand the transistor is opposite to that in FIG. 16A. That is, the firstpixel electrode 1088-1 is electrically connected to one of the sourceand the drain of the transistor 1081-2, and the second pixel electrode1088-2 is electrically connected to one of the source and the drain ofthe transistor 1081-1. Although not illustrated, each pixel electrode isconnected to a counter electrode through liquid crystal to form a liquidcrystal element.

Next, an estimate of how much the aperture ratio of each pixel in aliquid crystal display device is increased by using a thin filmtransistor including an oxide semiconductor layer according to oneembodiment of the present invention is shown.

Parameters for estimating the aperture ratio of a pixel are as follows:the peakage current of the thin film transistor including the oxidesemiconductor layer is 1×10⁻¹³ (A), the panel size is 3.4 inches, thegrayscale to be expressed is 256 gray levels, a voltage input is 10 V,and one frame for display is 1/60 second. Moreover, a gate insulatingfilm has a dielectric constant of 3.7 (F/m) and a thickness of 1×10⁻⁷(m).

First, the area of a capacitor and the aperture ratio in the case wherethe above-described parameters apply to a panel (referred to as a firstpanel) in which the number of pixels is 540×RGB×960 are estimated. Thesize of the pixel in the panel is 26 (μm)×78 (μm), that is, 2.03×10⁻⁹(m²). The area other than a region occupied by a wiring and a thin filmtransistor is 1.43×10⁻⁹ (m²), and the area of the region occupied by thewiring and the thin film transistor is 6.00×10⁻¹⁰ (m²).

In the first panel, a minimum necessary capacitance of an auxiliarycapacitor is 4.25×10⁻¹⁴ (F) in a pixel having a thin film transistorincluding an oxide semiconductor layer. In this case, the area necessaryfor the capacitor is 1.30×10⁻¹⁰ (m²); the capacitor accounts for 6.4% ofthe area of the pixel and the aperture ratio is 64.0%.

In addition, the area of a capacitor and the aperture ratio in the casewhere the above-described parameters apply to a panel (referred to as asecond panel) in which the number of pixels is 480×RGB×640 estimated.The size of a pixel in the panel is 36 (μm)×108 (μm), that is, 3.89×10⁻⁹(m²). The area excluding a region occupied by a wiring and a thin filmtransistor is 3.29×10⁻⁹ (m²), and the area of the region occupied by thewiring and the thin film transistor is 6.00×10⁻¹⁰ (m²).

In the second panel, a minimum necessary capacitance of an auxiliarycapacitor is 4.25×10⁻¹⁴ (F) in a pixel having a thin film transistorincluding an oxide semiconductor layer. In this case, the area necessaryfor the capacitor is 1.30×10⁻¹⁰ (m²); the capacitor accounts for 3.3% ofthe area of the pixel and the aperture ratio is 81.2%.

When a thin film transistor including an oxide semiconductor layeraccording to one embodiment of the present invention is used for thefirst panel and the second panel, a capacitor line can be reduced andthe region occupied by the pixel electrode 105 can be increased. Thecalculated aperture ratio in the first panel is 70.4% and that in thesecond panel is 84.5%; therefore, it is found that the aperture ratio issignificantly increased by omitting a capacitor.

By a combination of the pixel in this embodiment with the structure inEmbodiment 1 or 2, the aperture ratio can be increased when the pixelincluding a thin film transistor in which an oxide semiconductor is usedis formed.

This embodiment can be implemented in combination with any of thestructures described in the other embodiments as appropriate.

Embodiment 4

In this embodiment, an example of an electronic device including theliquid crystal display device described in any of Embodiments 1 to 3will be described.

FIG. 17A illustrates a portable game machine that can include a housing9630, a display portion 9631, speakers 9633, operation keys 9635, aconnection terminal 9636, a recording medium reading portion 9672, andthe like. The portable game machine in FIG. 17A can have a function ofreading a program or data stored in the recording medium to display iton the display portion, a function of sharing information with anotherportable game machine by wireless communication, and the like. Note thatthe portable game machine in FIG. 17A can have a variety of functionswithout being limited to the above.

FIG. 17B illustrates a digital camera that can include the housing 9630,the display portion 9631, the speakers 9633, the operation keys 9635,the connection terminal 9636, a shutter button 9676, an image receivingportion 9677, and the like. The digital camera having a televisionreception function in FIG. 17B can have various functions such as afunction of photographing a still image and/or a moving image; afunction of automatically or manually correcting the photographed image;a function of obtaining various kinds of information through an antenna;a function of storing the photographed image or the information obtainedthrough the antenna; and a function of displaying the photographed imageor the information obtained through the antenna on the display portion.Note that the digital camera having the television reception function inFIG. 17B can have a variety of functions without being limited to theabove.

FIG. 17C illustrates a television set that can include the housing 9630,the display portion 9631, the speakers 9633, the operation keys 9635,the connection terminal 9636, and the like. The television set in FIG.17C can have a function of converting an electric wave for televisioninto an image signal, a function of converting the image signal into asignal suitable for display, a function of converting a frame frequencyof the image signal, and the like. Note that the television set in FIG.17C can have a variety of functions without being limited to the above.

FIG. 18A illustrates a computer that can include the housing 9630, thedisplay portion 9631, the speaker 9633, the operation keys 9635, theconnection terminal 9636, a pointing device 9681, an external connectionport 9680, and the like. The computer in FIG. 18A can have a function ofdisplaying a variety of information (e.g., a still image, a movingimage, and a text image) on the display portion, a function ofcontrolling processing by a variety of software (programs), acommunication function such as wireless communication or wiredcommunication, a function of being connected to various computernetworks with the communication function, a function of transmitting orreceiving a variety of data with the communication function, and thelike. Note that the computer in FIG. 18A is not limited to having thesefunctions and can have a variety of functions.

FIG. 18B illustrates a mobile phone that can include the housing 9630,the display portion 9631, the speaker 9633, the operation keys 9635, amicrophone 9638, and the like. The mobile phone in FIG. 18B can have afunction of displaying a variety of information (e.g., a still image, amoving image, and a text image) on the display portion; a function ofdisplaying a calendar, a date, the time, or the like on the displayportion; a function of operating or editing the information displayed onthe display portion; a function of controlling processing by variouskinds of software (programs); and the like. Note that the functions ofthe mobile phone in FIG. 18B are not limited to those described above,and the mobile phone can have various functions.

FIG. 18C illustrates an electronic paper terminal (also referred to asan eBook or an e-book reader) that can include the housing 9630, thedisplay portion 9631, the operation keys 9635, and the like. Theelectronic paper in FIG. 18C can have a function of displaying a varietyof information (e.g., a still image, a moving image, and a text image)on the display portion; a function of displaying a calendar, a date, thetime, or the like on the display portion; a function of operating orediting the information displayed on the display portion; a function ofcontrolling processing by various kinds of software (programs); and thelike. Note that the electronic paper in FIG. 18C can have a variety offunctions without being limited to the above.

The electronic devices described in this embodiment each can include aliquid crystal display device in which the aperture ratio of a pluralityof pixels included in the display portion can be increased.

This embodiment can be implemented in combination with any of thestructures described in the other embodiments as appropriate.

This application is based on Japanese Patent Application serial no.2009-242787 filed with Japan Patent Office on Oct. 21, 2009, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a first conductivelayer comprising a region serving as one electrode of a capacitor; asecond conductive layer comprising a region serving as a gate electrode;an oxide semiconductor layer comprising a region overlapping with thegate electrode with a gate insulating layer therebetween; a thirdconductive layer electrically connected to the oxide semiconductor layerand comprising a region serving as one of a source electrode and a drainelectrode; an oxide insulating layer over the first conductive layer,the second conductive layer, the third conductive layer, and the oxidesemiconductor layer, the oxide insulating layer comprising a region incontact with a top surface of the oxide semiconductor layer; and a pixelelectrode electrically connected to the third conductive layer throughan opening portion of the oxide insulating layer, wherein a hydrogenconcentration in the oxide semiconductor layer is 5×10¹⁹/cm³ or less,wherein the first conductive layer comprises the same material as thesecond conductive layer, wherein the opening portion and the firstconductive layer overlap each other in a top view of the semiconductordevice, and wherein a region where the pixel electrode and the thirdconductive layer overlap each other entirely overlaps with the firstconductive layer in the top view of the semiconductor device.
 3. Asemiconductor device according to claim 2, wherein the oxidesemiconductor layer comprises indium, gallium, and zinc.
 4. Asemiconductor device according to claim 2, wherein a width of the oxidesemiconductor layer is larger than a width of the second conductivelayer in a cross-sectional view in a channel length direction of atransistor comprising the oxide semiconductor layer.
 5. A semiconductordevice according to claim 2, wherein each of the first conductive layerand the second conductive layer comprises copper.
 6. A semiconductordevice according to claim 2, wherein the semiconductor device is aliquid crystal display device.
 7. A semiconductor device comprising: afirst conductive layer comprising a region serving as one electrode of acapacitor; a second conductive layer comprising a region serving as agate electrode; an oxide semiconductor layer comprising a regionoverlapping with the gate electrode with a gate insulating layertherebetween; a third conductive layer electrically connected to theoxide semiconductor layer and comprising a region serving as one of asource electrode and a drain electrode; an oxide insulating layer overthe first conductive layer, the second conductive layer, the thirdconductive layer, and the oxide semiconductor layer, the oxideinsulating layer comprising a region in contact with a top surface ofthe oxide semiconductor layer; and a pixel electrode electricallyconnected to the third conductive layer through an opening portion ofthe oxide insulating layer, wherein the first conductive layer comprisesthe same material as the second conductive layer, wherein the openingportion and the first conductive layer overlap each other in a top viewof the semiconductor device, and wherein a region where the pixelelectrode and the third conductive layer overlap each other entirelyoverlaps with the first conductive layer in the top view of thesemiconductor device.
 8. A semiconductor device according to claim 7,wherein the oxide semiconductor layer comprises indium, gallium, andzinc.
 9. A semiconductor device according to claim 7, wherein a width ofthe oxide semiconductor layer is larger than a width of the secondconductive layer in a cross-sectional view in a channel length directionof a transistor comprising the oxide semiconductor layer.
 10. Asemiconductor device according to claim 7, wherein each of the firstconductive layer and the second conductive layer comprises copper.
 11. Asemiconductor device according to claim 7, wherein the semiconductordevice is a liquid crystal display device.
 12. A semiconductor devicecomprising: a first conductive layer comprising a region serving as oneelectrode of a capacitor; a second conductive layer comprising a regionserving as a gate electrode; an oxide semiconductor layer comprising aregion overlapping with the gate electrode with a gate insulating layertherebetween; a third conductive layer electrically connected to theoxide semiconductor layer and comprising a region serving as one of asource electrode and a drain electrode; a fourth conductive layercomprising a region serving the other of the source electrode and thedrain electrode; an oxide insulating layer over the first conductivelayer, the second conductive layer, the third conductive layer, and theoxide semiconductor layer, the oxide insulating layer comprising aregion in contact with a top surface of the oxide semiconductor layer;and a pixel electrode electrically connected to the third conductivelayer through an opening portion of the oxide insulating layer, whereinthe first conductive layer comprises the same material as the secondconductive layer, wherein the first conductive layer comprises a regionoverlapping with the fourth conductive layer in a top view of thesemiconductor device, wherein the opening portion and the firstconductive layer overlap each other in the top view of the semiconductordevice, and wherein a region where the pixel electrode and the thirdconductive layer overlap each other entirely overlaps with the firstconductive layer in the top view of the semiconductor device.
 13. Asemiconductor device according to claim 12, wherein the oxidesemiconductor layer comprises indium, gallium, and zinc.
 14. Asemiconductor device according to claim 12, wherein a width of the oxidesemiconductor layer is larger than a width of the second conductivelayer in a cross-sectional view in a channel length direction of atransistor comprising the oxide semiconductor layer.
 15. A semiconductordevice according to claim 12, wherein each of the first conductive layerand the second conductive layer comprises copper.
 16. A semiconductordevice according to claim 12, wherein the semiconductor device is aliquid crystal display device.